1. Field of the Invention
The present invention relates to an electronic circuit that is capable of suitably carrying out communications between chips such as IC (Integrated Circuit) bare chips to be stacked and mounted.
2. Description of the Related Arts
The present inventors have proposed electronic circuits that carry out communications by inductive coupling between chips to be stacked and mounted via coils formed by on-chip wiring of LSI (Large Scale Integration) chips (refer to Patent Documents 1 to 7 and Non-Patent Documents 1 to 3).
[Patent Document 1] US 20070289772 A1
[Patent Document 2] JP 2005-348264 A
[Patent Document 3] JP 2006-050354 A
[Patent Document 4] US 20070274198 A1
[Patent Document 5] JP 2006-105630 A
[Patent Document 6] US 20060176676 A1
[Patent Document 7] US 20060176624 A1
[Non-Patent Document 1] D. Mizoguchi et al., “A 1.2 Gb/s/pin Wireless Superconnect based on Inductive Inter-chip Signaling (IIS),” IEEE International Solid-State Circuits Conference (ISSCC '04), Dig. Tech. Papers, pp. 142-143, 517, February 2004.
[Non-Patent Document 2] N. Miura et al., “Analysis and Design of Transceiver Circuit and Inductor Layout for Inductive Inter-chip Wireless Superconnect,” Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 246-249, June 2004.
[Non-Patent Document 3] N. Miura et al., “Cross Talk Countermeasures in Inductive Inter-Chip Wireless Superconnect,” in Proc. IEEE Custom Integrated Circuits Conference (CICC '04), pp. 99-102, October 2004.